verilog: 10月 2015

10/28實作2

module top;

wire [3:0] OUT, A, B;
wire SEL;

system_clock #25600 clock1(A[0]);
system_clock #12800 clock2(A[1]);
system_clock #6400 clock3(A[2]);
system_clock #3200 clock4(A[3]);
system_clock #1600 clock5(SEL);
system_clock #800 clock6(B[0]);
system_clock #400 clock5(B[1]);
system_clock #200 clock6(B[2]);
system_clock #100 clock7(B[3]);

mux M32(OUT[3:2], A[3:2], B[3:2],SEL);
mux M10(OUT[1:0], A[1:0], B[1:0], SEL);
endmodule

module mux2(OUT, A, B, SEL);
output [1:0] OUT;
input [1:0] A,B;
input SEL;
mux hi (OUT[1], A[1], B[1], SEL);
mux lo (OUT[0], A[0], B[0], SEL);
endmodule

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL) ;

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule

10/28實作

module top;

wire SEL;

wire [2:0] A,B,OUT;

system_clock #800 clock1(A[2]);

system_clock #3200 clock2(A[1]);

system_clock #1600 clock3(A[0]);

system_clock #6400 clock4(SEL);

system_clock #400 clock5(B[2]);

system_clock #200 clock6(B[1]);

system_clock #100 clock7(B[0]);

mux M2(OUT[2], A[2], B[2], SEL);

mux2 M1(OUT[1:0], A[1:0], B[1:0], SEL);

endmodule

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL) ;

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule

module mux2(OUT, A, B, SEL);

output [1:0] OUT;

input [1:0] A,B;

input SEL;

mux hi (OUT[1], A[1], B[1], SEL);

mux lo (OUT[0], A[0], B[0], SEL);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

begin

#(PERIOD/2) clk=~clk;

end

always@(posedge clk)

if($time>6400)$stop;

endmodule

10/21實作

module top;

wire OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, OUT8, OUT9, A0, A1, A2, B0, B1,B2, SEL;
system_clock #100 clock1(SEL);

system_clock #200 clock2(A0);

system_clock #400 clock3(A1);

system_clock #800 clock4(A2);

system_clock #1600 clock5(B0);

system_clock #3200 clock6(B1);

system_clock #6400 clock7(B2);

not q1(NSEL, SEL);
and q2(OUT1, A1, SEL);
and q3(OUT2, B1, NSEL);
or q4(OUT3, OUT1, OUT2);

and q5(OUT4, A0, SEL);
and q6(OUT5, A2, SEL);
or q7(OUT6, OUT4, OUT5);

and q8(OUT7, B0, NSEL);
and q9(OUT8, B2, NSEL);
or q10(OUT9, OUT7, OUT8);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
begin
#(PERIOD/2) clk=~clk;
end

always@(posedge clk)
if($time>6400)$stop;