10/21實作

module top;


wire  OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, OUT8, OUT9, A0, A1, A2, B0, B1,B2, SEL;
system_clock #100 clock1(SEL);

system_clock #200 clock2(A0);

system_clock #400 clock3(A1);

system_clock #800 clock4(A2);

system_clock #1600 clock5(B0);

system_clock #3200 clock6(B1);

system_clock #6400 clock7(B2);

not q1(NSEL, SEL);
and q2(OUT1, A1, SEL);
and q3(OUT2, B1, NSEL);
or  q4(OUT3, OUT1, OUT2);

and q5(OUT4, A0, SEL);
and q6(OUT5, A2, SEL);
or  q7(OUT6, OUT4, OUT5);

and q8(OUT7, B0, NSEL);
and q9(OUT8, B2, NSEL);
or  q10(OUT9, OUT7, OUT8);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>6400)$stop;