期末機上考

module top;

wire A, B, C, D, A1, B1, C1, D1, OUT, OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, Q1, Q2, Q3, Q4, F;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);


nand a1(A1, A, A);
nand b1(B1, B, B);
nand c1(C1, C, C);
nand d1(D1, D, D);
nand a2(OUT,A1,B,C1,D);
nand a3(OUT1,OUT,OUT);
nand a4(OUT2,A1,C,D1);
nand a5(OUT3,OUT2,OUT2);
nand a6(OUT4,A,B,C);
nand a7(OUT5,OUT4,OUT4);
nand a8(OUT6,A,B1,D);
nand a9(OUT7,OUT6,OUT6);
nand a10(Q1,OUT1,OUT1);
nand a11(Q2,OUT3,OUT3);
nand a12(Q3,OUT5,OUT5);
nand a13(Q4,OUT7,OUT7);
nand a14(F,Q1,Q2,Q3,Q4);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

nor

module top;

wire A, B, C, D, F;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock1(C);
system_clock #100 clock2(D);


nor a1(A1,A,A);
nor a2(B1,B,B);
nor a3(C1,C,C);
nor a4(D1,D,D);
nor a5(A2,A,A);
nor a6(C2,C1,C1);
nor a7(D2,D1,D1);
nor a8(F4,A2,C2,D2);
nor a9(A3,A1,A1);
nor a10(B3,B1,B1);
nor a11(D3,D,D);
nor a12(F2,A3,B3,D3);
nor a13(B4,B,B);
nor a14(C4,C1,C1);
nor a15(D4,D1,D1);
nor a16(F3,B4,C4,D4);
nor a17(C5,C,C);
nor a18(D5,D,D);
nor a19(F1,C5,D5);
nor a20(F5,F1,F2,F3,F4);
nor a21(F,F5,F5);



endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

12/2 上機考 and

module top;

wire A, A0, B, B0, C, C0, D, D0, OUT, OUT1, OUT2, OUT3, OUT4;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);

not a1(A0, A);
not b1(B0, B);
not c1(C0, C);
not d1(D0, D);

and f1(OUT,A,C0,D0);
and f2(OUT1,A0,B0,D);
and f3(OUT2,B,C0,D0);
and f4(OUT3,C,D);
or  f5(OUT4,OUT,OUT1,OUT2,OUT3);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

12/2 上機考 nand

module top;

wire A, B, C, D, A1, B1, C1, D1, OUT, OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, Q1, Q2, Q3, Q4, F;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);


nand a1(A1, A, A);
nand b1(B1, B, B);
nand c1(C1, C, C);
nand d1(D1, D, D);
nand f1(OUT, A, C1, D1);
nand f2(OUT1, OUT, OUT);
nand f3(OUT2, A1, B1, D);
nand f4(OUT3, OUT2, OUT2);
nand f5(OUT4, B, C1, D1);
nand f6(OUT5, OUT4, OUT4);
nand f7(OUT6, C, D);
nand f8(OUT7, OUT6, OUT6);
nand f9(Q1, OUT1, OUT1);
nand f10(Q2, OUT3, OUT3);
nand f11(Q3, OUT5, OUT5);
nand f12(Q4, OUT7, OUT7);
nand f13(F,Q1,Q2,Q3,Q4);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

三位元全加法器 行為

module fulladder (sum, c_out, a, b, c_in);
wire s1, c1, c2;
output sum;
output c_out;
input a, b, c_in;

assign{c_out,sum}=a+b+c_in;
endmodule

module adder3(sum, c_out, a, b, c_in);
wire [2:0] c;
output [2:0] sum;
output c_out;
input [2:0] a;
input [2:0] b;
input c_in;
fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;
fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;
fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;


endmodule

module main;
reg [2:0] a;
reg [2:0] b;
wire [2:0] sum;
wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial
begin
  a = 4'b0101;
  b = 4'b0000;
end

always #50 begin
  b=b+1;
  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);
end

initial #2000 $finish;

endmodule

三位元全加法器 結構

module fulladder (sum, c_out, a, b, c_in);
wire s1, c1, c2;
output sum;
output c_out;
input a, b, c_in;
xor g1(s1, a, b);
xor g2(sum, s1, c_in);
and g3(c1, a,b);
and g4(c2, s1, c_in) ;
xor g5(c_out, c2, c1) ;

endmodule

module adder3(sum, c_out, a, b, c_in);
wire [2:0] c;
output [2:0] sum;
output c_out;
input [2:0] a;
input [2:0] b;
input c_in;
fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;
fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;
fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;


endmodule

module main;
reg [2:0] a;
reg [2:0] b;
wire [2:0] sum;
wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial
begin
  a = 4'b0101;
  b = 4'b0000;
end

always #50 begin
  b=b+1;
  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);
end

initial #2000 $finish;

endmodule

11/18 ADDER1

module top;
system_clock #400 clock1(C);
system_clock #200 clock2(A);
system_clock #100 clock3(B);

adder1 m1(A, B, C, Cout, Sum);

endmodule

module adder1(A, B, C,Cout,Sum);
output Cout, Sum;
input A, B, C;
not I1(Anot,A);
not I2(Bnot,B);
not I3(Cnot,C);

and I4(S1,A,B);
and I5(S2,B,C);
and I6(S3,A,C);
and I7(S4,A,B,C);
and I8(S5,A,Bnot,Cnot);
and I9(S6,Anot,B,Cnot);
and I10(S7,Anot,Bnot,C);

or I11(Cout,S1,S2,S3);
or I12(Sum,S4,S5,S6,S7);

endmodule