nor

module top;

wire A, B, C, D, F;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock1(C);
system_clock #100 clock2(D);


nor a1(A1,A,A);
nor a2(B1,B,B);
nor a3(C1,C,C);
nor a4(D1,D,D);
nor a5(A2,A,A);
nor a6(C2,C1,C1);
nor a7(D2,D1,D1);
nor a8(F4,A2,C2,D2);
nor a9(A3,A1,A1);
nor a10(B3,B1,B1);
nor a11(D3,D,D);
nor a12(F2,A3,B3,D3);
nor a13(B4,B,B);
nor a14(C4,C1,C1);
nor a15(D4,D1,D1);
nor a16(F3,B4,C4,D4);
nor a17(C5,C,C);
nor a18(D5,D,D);
nor a19(F1,C5,D5);
nor a20(F5,F1,F2,F3,F4);
nor a21(F,F5,F5);



endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule