12/2 上機考 and

module top;

wire A, A0, B, B0, C, C0, D, D0, OUT, OUT1, OUT2, OUT3, OUT4;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);

not a1(A0, A);
not b1(B0, B);
not c1(C0, C);
not d1(D0, D);

and f1(OUT,A,C0,D0);
and f2(OUT1,A0,B0,D);
and f3(OUT2,B,C0,D0);
and f4(OUT3,C,D);
or  f5(OUT4,OUT,OUT1,OUT2,OUT3);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule