期末機上考

module top;

wire A, B, C, D, A1, B1, C1, D1, OUT, OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, Q1, Q2, Q3, Q4, F;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);


nand a1(A1, A, A);
nand b1(B1, B, B);
nand c1(C1, C, C);
nand d1(D1, D, D);
nand a2(OUT,A1,B,C1,D);
nand a3(OUT1,OUT,OUT);
nand a4(OUT2,A1,C,D1);
nand a5(OUT3,OUT2,OUT2);
nand a6(OUT4,A,B,C);
nand a7(OUT5,OUT4,OUT4);
nand a8(OUT6,A,B1,D);
nand a9(OUT7,OUT6,OUT6);
nand a10(Q1,OUT1,OUT1);
nand a11(Q2,OUT3,OUT3);
nand a12(Q3,OUT5,OUT5);
nand a13(Q4,OUT7,OUT7);
nand a14(F,Q1,Q2,Q3,Q4);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule