12/2 上機考 nand

module top;

wire A, B, C, D, A1, B1, C1, D1, OUT, OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, Q1, Q2, Q3, Q4, F;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);


nand a1(A1, A, A);
nand b1(B1, B, B);
nand c1(C1, C, C);
nand d1(D1, D, D);
nand f1(OUT, A, C1, D1);
nand f2(OUT1, OUT, OUT);
nand f3(OUT2, A1, B1, D);
nand f4(OUT3, OUT2, OUT2);
nand f5(OUT4, B, C1, D1);
nand f6(OUT5, OUT4, OUT4);
nand f7(OUT6, C, D);
nand f8(OUT7, OUT6, OUT6);
nand f9(Q1, OUT1, OUT1);
nand f10(Q2, OUT3, OUT3);
nand f11(Q3, OUT5, OUT5);
nand f12(Q4, OUT7, OUT7);
nand f13(F,Q1,Q2,Q3,Q4);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule