11/4 一位元多工器

module top;
  integer ia,ib,is;
  reg  a,b,s;
  wire out;

  mux_behavioral mux1(out,a,b,s);

  initial
    begin
      for (is=0; is<=1; is = is+1)
        begin
          s = is;
          for (ib=0; ib<=1; ib = ib + 1)
            begin
              b = ib;
              for (ia=0; ia<=1; ia = ia + 1)
               begin
                 a = ia;
                 #10 $display("s=%d b=%d a=%d   out=%d",s,b,a,out);
               end
            end
        end
    end
endmodule
module mux_behavioral(OUT, A, B, SEL);
 output OUT;
 input A,B,SEL;
 wire  A,B,SEL;
 reg    OUT;

  always @(A or B or SEL)
   OUT = (A & SEL)|(B & ~SEL );
endmodule